65C02 Reference Manual

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Table of Contents:

  1. General Overview
  2. Instruction Set
  3. Addressing Modes
  4. Instruction Encodings
  5. Examples

General Overview

The Western Design Center, Inc. (WDC) of Mesa, AZ, is the original designer and intellectual property owner of the 65C02. You can get official information about WDC and their products by visiting their web page.

The 65C02 has a 16 bit address space (64K) arranged in 256 pages each of which is 256 bytes long.

Page 0 ($0000-$00FF) has some special properties involving addressing modes and is very valuable memory.

Page 1 ($0100-$01FF) is the stack.

Bytes $FFFA-$FFFB are the NMIB interrupt vector.
Bytes $FFFC-$FFFD are the reset vector.
Bytes $FFFE-$FFFF are the IRQ/BRK vector.

The 65C02 has 3 registers, stack pointer, processor flags (P), and program counter. The registers are the Accumulator (A), X index, and Y index. Each is 8 bits wide. Most instructions leave results in the accumulator. The stack pointer is an 8 bit register that is used as an offset into the stack (page 1). It is auto incrementing and decrementing when used with the push and pull (pop) instructions. You can also directly access and modify it's value via the TSX and TXS instructions.

The P register contains the following one bit flags:

Negative (N)
Set when the result of an operation leaves the high bit set. Cleared otherwise.
Overflow (V)
Set when there is a borrow or carry out of an operation.
Break (B)
Set when a 'BRK' instruction is encountered.
Decimal (D)
When set all arithmatic is BCD (ie. 09+01=10). When clear all arithmatic is binary 2s complement (ie. 09+01=0A).
Interrupt Disable (I)
When set no interrupts can occur.
Zero (Z)
Set when the result of an operation is zero. Cleared otherwise.
Carry (C)
Set when there is a carry. (more here)
The bit's are arranged as follows (from 7 [highest] to 0 [lowest]): NV-BDIZC

Instruction Set

Load & Store Instructions
LDAload accumulatorNZ
LDXload X indexNZ
LDYload Y indexNZ
STAstore accumulator-
STXstore X index-
STYstore Y index-
STZstore zero-
Stack Operations
PHApush accumulator-
PHXpush X index-
PHYpush Y index-
PHPpush processor flags-
PLApull (pop) accumulatorNZ
PLXpull (pop) X indexNZ
PLYpull (pop) Y indexNZ
PLPpull (pop) processor flagsAll
TSXtransfer stack pointer to XNZ
TXStransfer X to stack pointer-
Increment & Decrement Operations
INAincrement accumulatorNZ
INXincrement X indexNZ
INYincrement Y indexNZ
DEAdecrement accumulatorNZ
DEXdecrement X indexNZ
DEYdecrement Y indexNZ
INCincrement memory locationNZ
DECdecrement memory locationNZ
Shift Operations
ASLarithmetic shift left, high bit into carryNZC
LSRlogical shift right, low bit into carryN=0 ZC
ROLrotate left through carryNZC
RORrotate right through carryNZC
Logical Operations
ANDand accumulatorNZ
ORAor accumulatorNZ
EORexclusive-or accumulatorNZ
BITtest bits against accumulator (1)N=M7 V=M6 Z
CMPcompare with accumulatorNZC
CPXcompare with X indexNZC
CPYcompare with Y indexNZC
TRBtest and reset bitsx
TSBtest and set bitsx
RMBreset memory bitx
SMBreset memory bitx
Math Operations
ADCadd accumulator, with carryNZCV
SBCsubtract accumulator, with borrowNZCV
Flow Control Instructions
JMPunconditional jump-
JSRjump Subroutine-
RTSreturn from Subroutine-
RTIreturn from InterruptFrom Stack
BRAbranch Always-
BEQbranch on equal (zero set)-
BNEbranch on not equal (zero clear)-
BCCbranch on carry clear (2)-
BCSbranch on carry set (2)-
BVCbranch on overflow clear-
BVSbranch on overflow set-
BMIbranch on minus-
BPLbranch on plus-
BBRbranch on bit reset (zero)-
BBSbranch on bit set (one)-
Processor Status Instructions
CLCclear carry flagC=0
CLDclear decimal modeD=0
CLIclear interrupt disable bitI=0
CLVclear overflow flagV=0
SECset carry flagC=1
SEDset decimal modeD=1
SEIset interrupt disable bitI=1
Transfer Instructions
TAXtransfer accumulator to X indexNZ
TAYtransfer accumulator to Y indexNZ
TXAtransfer X index to accumulatorNZ
TYAtransfer Y index to accumulatorNZ
Misc Instructions
NOPno operation-
BRKforce breakB=1


  1. The BIT instruction copies bit 6 to the V flag, and bit 7 to the N flag (except in immediate addressing mode where V & N are untouched.) The accumulator and the operand are ANDed and the Z flag is set appropriately.
  2. The BCC & BCS instructions instructions are sometimes known as BLT (branch less than) and BGE (branch greater or equal), respectively.

Addressing Modes

There are fifteen addressing modes available. They are:
Implied Addressing [Implied]
In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the intruction.
Accumulator Addressing [Accumulator]
This form of addressing is represented with a one byte instruction and implies an operation on the accumulator.
Immediate Addressing [Immediate]
With immediate addressing, the operand is contained in the second byte of the instruction; no further memory addressing is required.
Absolute Addressing [Absolute]
For absolute addressing, the second byte of the instruction specifies the eight low-order bits of the effective address, while the third byte specifies the eight high-order bits. Therefore, this addressing mode allows access to the total 64K bytes of addressable memory.
Zero Page Addressing [Zero Page]
Zero page addressing allows shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. The careful use of zero page addressing can result in significant increase in code efficiency.
Absolute Indexed Addressing [Absolute,X or Absolute,Y]
Absolute indexed addressing is used in conjunction with X or Y index register and is referred to as "Absolute, X," and "Absolute, Y." The effective address is formed by adding the contents of X or Y to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields, resulting in reduced coding and instruction time.
Zero Page Indexed Addressing [Zero Page,X or Zero Page,Y]
Zero page indexed addressing is used in conjunction with the index register and is referred to as "Zero Page, X" or "Zero Page, Y." The effective address is calculated by adding the second byte to the contents of the indexed register. Since this is a form of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally, due to the "Zero Page" addressing nature of this mode, no carry is added to the high-order eight bits of memory, and crossing of page boundaries does not occur.
Relative Addressing [Relative]
Relative addressing is used only with branch instructions; it establishes a destination for the conditional branch. The second byte of the instruction becomes the operand which is an "Offset" added to the contents of the program counter when the program counter is set at the next instruction. The range of the offset is -128 to 127 bytes from the next instruction.
Zero Page Indexed Indirect Addressing [(Zero Page,X)]
With zero page indexed indirect addressing (usually referred to as indirect X) the second byte of the instruction is added to the contents of the X index register; the carry is discarded. The result of this addition points to a memory location on page zero whose contents is the low-order eight bits of the effective address. The next memory location in page zero contains the high-order eight bits of the effective address. Both memory locations specifying the high- and low-order bytes of the effective address must be in page zero.
Absolute Indexed Indirect Addressing [(Absolute,X)]
(Jump Instruction Only) With absolute indexed indirect addressing the contents of the second and third instruction bytes are added to the X register. The result of this addition, points to a memory location containing the low-order eight bits of the effective address. The next memory location contains the higher-order eight bits of the effective address.
Indexed Indirect Addressing [(Zero Page),Y]
This form of addressing is usually referred to as Indirect, Y. The second byte of the instruction points to a memory location in page zero. The contents of this memory location are added to the Y index register, the result being the low-order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location, the result being the high-order eight bits of the effective address.
Zero Page Indirect Addressing [(Zero Page)]
In the zero page indirect addressing mode, the second byte of the instruction points to a memory location on page zero containing the low-order byte of the effective address. The next location on page zero contains the high-order byte of the effective address.
Absolute Indirect Addressing [(Absolute)]
(Jump Instruction Only) The second byte of the instruction contains the low-order eight bits of a memory location. The high-order eight bits of that memory location is contained in the third byte of the instruction. The contents of the fully specified memory location is the low-order byte of the effective address. The next memory location contains the high-order byte of the effective address which is loaded into the 16 bit program counter.

Instruction Encodings

MnemonicAddressing modeFormOpcodeSizeTiming
ADCImmediateADC #Oper6922
Zero PageADC Zpg6523
Zero Page,XADC Zpg,X7524
AbsoluteADC Abs6D34
Absolute,XADC Abs,X7D34
Absolute,YADC Abs,Y7934
(Zero Page,X)ADC (Zpg,X)6126
(Zero Page),YADC (Zpg),Y7125
(Zero Page)ADC (Zpg)7225
ANDImmediateAND #Oper2922
Zero PageAND Zpg2523
Zero Page,XAND Zpg,X3524
AbsoluteAND Abs2D34
Absolute,XAND Abs,X3D34
Absolute,YAND Abs,Y3934
(Zero Page,X)AND (Zpg,X)2126
(Zero Page),YAND (Zpg),Y3125
(Zero Page)AND (Zpg)3225
ASLAccumulatorASL A0A12
Zero PageASL Zpg0625
Zero Page,XASL Zpg,X1626
AbsoluteASL Abs0E36
Absolute,XASL Abs,X1E37
BBR0RelativeBBR0 Oper0F22
BBR1RelativeBBR1 Oper1F22
BBR2RelativeBBR2 Oper2F22
BBR3RelativeBBR3 Oper3F22
BBR4RelativeBBR4 Oper4F22
BBR5RelativeBBR5 Oper5F22
BBR6RelativeBBR6 Oper6F22
BBR7RelativeBBR7 Oper7F22
BBS0RelativeBBS0 Oper8F22
BBS1RelativeBBS1 Oper9F22
BBS2RelativeBBS2 OperAF22
BBS3RelativeBBS3 OperBF22
BBS4RelativeBBS4 OperCF22
BBS5RelativeBBS5 OperDF22
BBS6RelativeBBS6 OperEF22
BBS7RelativeBBS7 OperFF22
BCCRelativeBCC Oper9022
BCSRelativeBCS OperB022
BEQRelativeBEQ OperF022
BITImmediateBIT #Oper8922
Zero PageBIT Zpg2423
Zero Page,XBIT Zpg,X3424
AbsoluteBIT Abs2C34
Absolute,XBIT Abs,X3C34
BMIRelativeBMI Oper3022
BNERelativeBNE OperD022
BPLRelativeBPL Oper1022
BRARelativeBRA Oper8023
BVCRelativeBVC Oper5022
BVSRelativeBVS Oper7022
CMPImmediateCMP #OperC922
Zero PageCMP ZpgC523
Zero Page,XCMP ZpgD524
AbsoluteCMP AbsCD34
Absolute,XCMP Abs,XDD34
Absolute,YCMP Abs,YD934
(Zero Page,X)CMP (Zpg,X)C126
(Zero Page),YCMP (Zpg),YD125
(Zero Page)CMP (Zpg)D225
CPXImmediateCPX #OperE022
Zero PageCPX ZpgE423
AbsoluteCPX AbsEC34
CPYImmediateCPY #OperC022
Zero PageCPY ZpgC423
AbsoluteCPY AbsCC34
DECZero PageDEC ZpgC625
Zero Page,XDEC Zpg,XD626
AbsoluteDEC AbsCE36
Absolute,XDEC Abs,XDE37
EORImmediateEOR #Oper4922
Zero PageEOR Zpg4523
Zero Page,XEOR Zpg,X5524
AbsoluteEOR Abs4D34
Absolute,XEOR Abs,X5D34
Absolute,YEOR Abs,Y5934
(Zero Page,X)EOR (Zpg,X)4126
(Zero Page),YEOR (Zpg),Y5125
(Zero Page)EOR (Zpg)5225
INCZero PageINC ZpgE625
Zero Page,XINC Zpg,XF626
AbsoluteINC AbsEE36
Absolute,XINC Abs,XFE37
JMPAbsoluteJMP Abs4C33
(Absolute)JMP (Abs)6C35
(Absolute,X)JMP (Abs,X)7C36
JSRAbsoluteJSR Abs2036
LDAImmediateLDA #OperA922
Zero PageLDA ZpgA523
Zero Page,XLDA Zpg,XB524
AbsoluteLDA AbsAD34
Absolute,XLDA Abs,XBD34
Absolute,YLDA Abs,YB934
(Zero Page,X)LDA (Zpg,X)A126
(Zero Page),YLDA (Zpg),YB125
(Zero Page)LDA (Zpg)B225
LDXImmediateLDX #OperA222
Zero PageLDX ZpgA623
Zero Page,YLDX Zpg,YB624
AbsoluteLDX AbsAE34
Absolute,YLDX Abs,YBE34
LDYImmediateLDY #OperA022
Zero PageLDY ZpgA423
Zero Page,YLDY Zpg,XB424
AbsoluteLDY AbsAC34
Absolute,YLDY Abs,XBC34
LSRAccumulatorLSR A4A12
Zero PageLSR Zpg4625
Zero Page,XLSR Zpg,X5626
AbsoluteLSR Abs4E36
Absolute,XLSR Abs,X5E37
ORAImmediateORA #Oper0922
Zero PageORA Zpg0523
Zero Page,XORA Zpg,X1524
AbsoluteORA Abs0D34
Absolute,XORA Abs,X1D34
Absolute,YORA Abs,Y1934
(Zero Page,X)ORA (Zpg,X)0126
(Zero Page),YORA (Zpg),Y1125
(Zero Page)ORA (Zpg)1225
ROLAccumulatorROL A2A12
Zero PageROL Zpg2625
Zero Page,XROL Zpg,X3626
AbsoluteROL Abs2E36
Absolute,XROL Abs,X3E37
RORAccumulatorROR A6A12
Zero PageROR Zpg6625
Zero Page,XROR Zpg,X7626
AbsoluteROR Abs6E36
Absolute,XROR Abs,X7E37
SBCImmediateSBC #OperE922
Zero PageSBC ZpgE523
Zero Page,XSBC Zpg,XF524
AbsoluteSBC AbsED34
Absolute,XSBC Abs,XFD34
Absolute,YSBC Abs,YF934
(Zero Page,X)SBC (Zpg,X)E126
(Zero Page),YSBC (Zpg),YF125
(Zero Page)SBC (Zpg)F225
STAZero PageSTA Zpg8523
Zero Page,XSTA Zpg,X9524
AbsoluteSTA Abs8D34
Absolute,XSTA Abs,X9D35
Absolute,YSTA Abs,Y9935
(Zero Page,X)STA (Zpg,X)8126
(Zero Page),YSTA (Zpg),Y9126
(Zero Page)STA (Zpg)9225
STXZero PageSTX Zpg8623
Zero Page,YSTX Zpg,Y9624
AbsoluteSTX Abs8E34
STYZero PageSTY Zpg8423
Zero Page,XSTY Zpg,X9424
AbsoluteSTY Abs8C34
STZZero PageSTZ Zpg6423
Zero Page,XSTZ Zpg,X7424
AbsoluteSTZ Abs9C34
Absolute,XSTZ Abs,X9E35
TRBZero PageTRB Zpg1425
AbsoluteTRB Abs1C36
TSBZero PageTSB Zpg0425
AbsoluteTSB Abs0C36


For examples please go back to the main page and look at the "Useful/Interesting Code Snippets" section.